- The duration of a regular paper presentation is 30 minutes, which contains a lecture for about 20 minutes and about 10 minutes for questions from the audience.
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- Please DOWNLOAD the template of powerpoint for your further reference.
- The duration of a regular paper presentation is 10 minutes, which contains a lecture for about 5 minutes and about 5 minutes for questions from the audience.
- If you do the presentation online, please submit a record through HERE by June 30, 2023. You are required to do the presentation ONLINE, and the recrod will be played only if your internet is not stable.
- Besides, please prepare a poster for onsite display with the size of A0 (1189 highx841 base). The conference organizers can print the poster for you if it is sent to us before June 30, 2023 (by email async2023@youngac.cn with your paper ID as the subject). Otherwise, please print and bring it along with you to the conference.
Presentation Guideline
Program at a Glance
| July 16 （Sunday） | ||
| 10:00-17:00 | Registration | |
| July 17 （Monday） | ||
| 8:30-8:50 | Openning Ceremony | |
| 8:50-9:50 | Keynote Speech |
Mike Davies, Neuromorphic Computing
Laboratory, Intel Corporation, USA Title: TBA |
| 9:50-10:10 | Coffee Break | |
| Session 1 : Asynchronous Pipelines, Test, Security, Fault Tolerance, and Case Sudy | ||
| 10:10-10:40 | 820 |
A Novel Asynchronous Network-on-chip Based
on Source Asynchronous Signaling Venkata Sai Madhukiran Harsha Nori1, Baudouin Chauviere1, Mackenzie Wibbels1 and Kenneth Stevens1 1University of Utah, United States |
| 10:40-10:50 |
3912 (Fresh Idea) |
Quasi-synchronous Communication on SoC Zeng Qingyang1, Wang Jingyu1, Cong Jiaxu1, Dai Yue2, Tang Xiqin2, Li Yang2 and Shang Delong3 1Institute of Microelectronics, Chinese Academic of Sciences,China; 2Nanjing Institute of Intelligent and Technology,China; 3Nanjing Institute of Intelligent and Technology Institute of Microelectronics, Chinese Academic of Sciences, China |
| 10:50-11:20 | 2247 |
Verification-driven Design for Asynchronous
VLSI Xiang Wu1 and Rajit Manohar1 1Yale University, United States |
| 11:20-11:50 | 6636 |
Case Study for Skewing MTNCL Circuits Cole Sherrill1, Kyle Orman1, Nicholas Brown1 and Jia Di1 1University of Arkansas, United States |
| 12:00-14:00 | Lunch | |
| 14:00-15:00 | Keynote Speech |
Yvain Thonnart, CEA Leti, France Title: TBA |
| Session 2: CAD Tools for Asynchronous Design, Synthesis, Analysis, and Optimization | ||
| 15:00-15:30 | 3119 |
Design Asynchronous Circuits with Chisel Jilin Zhang1, Chunqi Qian1, Dexuan Huo1, Jian Zhang1 and Hong Chen1 1Tsinghua University, China |
| 15:30-16:00 | 7079 |
Yak: An Asynchronous Bundled Data Pipeline
Description Language Carsten Nielsen1, Zhe Su1 and Giacomo Indiveri1 1University of Zurich and ETH Zurich, Switzerland |
| 16:00-16:10 |
4371 (Fresh Idea) |
CanMore: A Configurable Asynchronous
Neuromorphic Hardware Simulator Jian Zhang1 and Hong Chen1 1Tsinghua University, China |
| 16:10-16:30 | Coffee Break | |
| Session 3 : Asynchronous Pipelines, Architectures, CPUs, and Circuits | ||
| 16:30-17:00 | 7458 |
A Novel Approach for Mitigating Single Event
Transient Effects in Quasi Delay Insensitive Logic Zaheer Tabassam1, Andreas Steininger1, Robert Najvirt1 and Florian Huemer1 1TU Wien, Austria |
| 17:00-17:10 |
6479 (Fresh Idea) |
Data-driven Pruning for Bundled-data
Circuits Cristiano Merio1, Xavier Lesage, Ali Naimi2, 1Sylvain Engels1, Katell Morin-Allory3 and Laurent Fesquet3 1Grenoble-INP / TIMA & STMicrolectronics, France; 2Grenoble-INP / TIMA & Orioma, France; 3Grenoble-INP / TIMA,France |
| 17:10-17:40 | 6840 |
A Smart Event-based Vision Sensor with a
320K Neuron Convolutional Neuronal Network Processing Pipeline Ole Richter1, Yannan Xing2, Michele De Marchi3, Carsten Nielsen3, Merkourios Katsimpris3, Roberto Cattaneo3, Yudi Ren2, Yalun Hu2, Qian Liu3, Sadique Sheik3, Tugba Demirci3 and Ning Qiao3 1University of Groningen, Netherlands; 2Synsense, China; 3Synsense AG, China |
| 17:40-17:50 |
6069 (Fresh Idea) |
A 22nm Asynchronous RISC-V Processor with
Self-adaptive Pipeline and Asynchronous Cache Module Mingxuan Liang 1and Hong Chen1 1Tsinghua University，China |
| 17:50-18:00 |
7162 (Fresh Idea) |
SLAD: A Low-power Microprocessor
Architecture Based on Synchronous Logic Asynchronous Driven
Mechanism Zhenbang Kang1, Yihua Lu1, Zecheng Liang1, Ruoyun Sun1 and Anping He1 1Lanzhou University, China |
| 18:00-20:00 | Banquet | |
| July 18 (Tuesday) | ||
| 8:30-9:30 | Keynote Speech |
Kanwen (Kevin) Wang, Huawei Technologies
Co., Ltd., China Title: Our Practice and Expectations on Asynchronous Design |
| 9:30-10:20 | Special Session Speech |
Huaqiang Wu, Tsinghua University, China Title: Memristor-based Energy-efficient Neuromorphic Computing |
| 10:20-10:40 | Coffee Break | |
| 10:40-11:30 | Special Session Speech |
Elisabetta Chicca, University of Groningen,
The Netherlands Title: TBA |
| 11:30-12:20 | Special Session Speech |
Gang Pan, Zhejiang University, China Title: Neuromorphic Computer: Progresses, Challenges, and Practices |
| 12:20-14:00 | Lunch | |
| 14:00-18:00 | Field Trip to Forbidden City | |
| 18:30-20:00 | Dinner | |
| July 19 (Wednesday) | ||
| 8:30-10:00 | Tutorial |
Rajit Manohar, Computer Systems Lab at Yale,
USA Title: An ASIC Flow for Asynchronous Logic |
| 10:00-10:10 | Coffee Break | |
| Session 4: Formal Methods for Verification and Performance/Power Analysis | ||
| 10:10-10:40 | 7309 |
Cyclic Timing Path Evaluation Using
Commercial Static Timing Analysis Algorithms Mac Wibbels1, Baudouin Chauviere1, Kenneth Stevens1 1University of Utah, United States |
| 10:40-11:10 | 1686 |
Timed Signalling Processes Rajit Manohar1 and Yoram Moses2 1Yale Univerisity, United States; 2Technion-Israel Institute of Technology, Israel |
| 11:10-11:40 | 3540 |
Opportunistic Mutual Exclusion Karthi Srinivasan1, Yoram Moses2 and Rajit Manohar1 1Yale University, United States; 2Technion-Israel Institute of Technology, Israel |
| 11:40-12:10 |
2050 (Industrial Paper) |
A QDI Interconnect for 3D Systems Using
Industry Standard EDA and Cell Libraries Matheus Trevisan Moreira1, William Koven1, Tony Wu1, Ekin Sumbul1 and Edith Beigne1 1Reality Labs, Meta (Formerly known as Facebook Inc), United States |
| 12:10-14:00 | Lunch | |
| Session 5: Asynchronous Design for Neural Networks and Machine Learning Applications | ||
| 14:00-14:30 | 9150 |
Core Interface Optimization for Multi-core
Neuromorphic Processors Zhe Su1, Hyunjung Hwang2, Tristan Torchet2 and Giacomo Indiveri1 1Institute of Neuroinformatics University of Zurich and ETH Zurich, Switzerland; 2ETH Zurich, Switzerland |
| 14:30-15:00 | 6672 |
An Efficient Data Structure for Sparse
Bit-sets with Applications in Neuromorphic Computing Prafull Purohit1, Johannes Leugering2 and Rajit Manohar1 1Yale University, United States; 2Fraunhofer Insititute for Integrated Circuits (IIS), Germany |
| 15:00-15:30 | 9680 |
A 28nm Energy-efficient Asynchronous SNN
Accelerator with On-chip Learning for Gas Recognition Dexuan Huo1, Jilin Zhang1 and Hong Chen1 1Tsinghua university, China |
| 15:30-15:50 | Coffee Break | |
| Session 6: Mixed-timed Circuits, Clock Domain Crossing, GALS Systems, Network-on-chip, and Multi-chip Interconnects | ||
| 15:50-16:00 |
3058 (Fresh Idea) |
Analysis of GasP Asynchronous Handshake
Circuit Based on Logical Effort Xun Li1, Yan Wang1, Mingyang Zhou1 and Anping He1 1Lanzhou University, China |
| 16:00-16:30 | 8273 |
Flexible Compilation and Refinement of
Asynchronous Circuits Ebelechukwu Esimai1 and Marly Roncken1 1Portland State University, United States |
| 16:30-17:00 |
2566 (Industrial Paper) |
Live Demonstration: Low Power and High Speed
AI on an Asynchronous Neuromorphic ASIC Yannan Xing1, Yuhsien Fan1, Nogay Kuepelioglu2, Yalun Hu1, Michele De Marchi2, Carsten Nielsen2, Yudi Ren1, Sadique Sheik2, Tugba Demirci2 and Ning Qiao1 1SynSense, China; 2SynSense, Switzerland |
| 17:00-17:30 | Best Paper Award Ceremony and Closing Ceremony | |
| 18:00-20:00 | Dinner | |