Mike Davies

Neuromorphic Computing Laboratory, Intel Corporation, USA

Bio: Mike Davies has led the design and development of many of the industry’s most advanced asynchronous chips over the past 23 years. As Fulcrum Microsystems’ Director of Silicon Engineering, he and his team pioneered high performance, commercially viable asynchronous design methodologies. Over that time, Fulcrum produced five generations of switch products with leading bandwidth, latency, power, and features. Today, as Director of Intel’s Neuromorphic Computing Lab, he continues to advance asynchronous design practice, most visibly with its application to the Loihi series of neuromorphic research chips.

Speech Title: Go Big or Go Home

After decades of research and a handful of commercial applications, asynchronous design remains a niche methodology at the fringe of the semiconductor industry. The reasons for this are well known: lack of EDA tool support, lack of standardization, limited literature quantifying sync-versus-async tradeoffs, and a “black art” reputation with little mainstream awareness. Asynchronous circuits can outperform synchronous circuits, but in most cases the gains are insufficient to overcome the costs of deviating from standard synchronous methods. For this to change and for asynchronous design to thrive, a compelling killer app is needed – a new class of computing device in which the benefits of asynchrony overwhelm the cost of synchronization at the circuit level. Biological neural circuits in the brains of animals have that characteristic, perhaps the only known example. In this talk I will describe the deep synergies between asynchronous design and neuromorphic chips inspired by biological neural networks. Arguably the fates of these two technologies are fundamentally linked.

Yvain Thonnart

CEA-List, France

Bio: Yvain Thonnart received the MS degree from Ecole Polytechnique and an engineering diploma from Telecom Paris, France in 2005. He then joined the Technological Research Division of CEA, the French French Alternative Energies and Atomic Energy Commission, within the CEA-Leti institute until 2019, then within the CEA-List institute. He has led the development of several large research projects for on-chip communications, focusing on the maturation of novel concepts towards industrial adoption, such as CEA’s ANOC asynchronous network on chip, communication between multiple voltage and frequency domains, 3D-stacked circuits, and optical on-chip interconnects, leading to more than 70 publications and 10 patents. He is now senior expert on communication and synchronization in systems on chip, and scientific advisor for the mixed-signal design lab. His main research interests include asynchronous logic, networks on chip, physical implementation, emerging technologies integration such as photonics, cryoelectronics and interposers. He is currently serving in the technical program committee of the ISSCC.

Speech Title: The ANOC Asynchronous Communication Architecture: a Retrospective on a 15-year Circuit Roadmap

Developments on the ANOC communication architecture started at CEA in 2004, driven by the momentum on networks on chip at the time, and leveraging a strong background in the asynchronous design community. The ANOC backbone is implemented using Quasi Delay Insensitive asynchronous logic, and integrates many features : routers, links, GALS interfaces, methodology, etc. Since the early beginning, it has gone through several generations of technology, implementation and architecture. Its deployment into several prototyping platforms, from heterogeneous dataflow accelerators to industrial test-case SoCs and massively parallel computing architectures led to multiple evolutions of ANOC including IP maturation and new features, design methodology, power management, and up to implementations using 3D technology and chiplet integration. In this talk, we will look back at those developments and highlight the driving motivation for these evolutions, to extract the key lessons learned from the application of ANOC to several process nodes and prototyping platforms, and aim to project such lessons into new perspectives for the research community and guidelines towards acceptance by the industry.

Kanwen (Kevin) Wang

Huawei Technologies Co., Ltd., China

Bio: Kanwen (Kevin) Wang received the B.S. and Ph.D degree in microelectronics from Fudan University, Shanghai, China, in 2006 and 2012, respectively. From 2012 to 2014, he has been a research fellow at the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore. Since November 2014, he joined 2012 Labs, Central Research Institute, Huawei Technologies Co., Ltd. Now he is a principal engineer at Advanced Computing and Storage Lab, in charge of the asynchronous circuit design for brain-inspired computing architecture. His primary research interests include asynchronous design and applications, emerging device technologies for computing-in-memory and event camera systems.

Speech Title: Our Practice and Expectations on Asynchronous Design

The advent of event-driven bio-inspired computing has led to the resurgence of asynchronous design. This presentation reviews the latest progress on two mainstream asynchronous design techniques: quasi-delay insensitive (QDI) and bundled data (BD). Besides, we will show our asynchronous design practice on neuromorphic computing architecture using these two techniques. On the other hand, we are also exploring some potential asynchronous opportunities, aiming to achieve better power, latency, throughput compared to the synchronous counterpart. Design challenges and our expectations will be discussed in the end.

Giacomo Indiveri

University of Zurich and ETH Zurich, Switzerland

Bio: Giacomo Indiveri (Senior Member, IEEE) received the M.Sc. degree in electrical engineering and the Ph.D. degree in computer science and electrical engineering from the University of Genova, Genova, Italy, in 1992 and 2004, respectively.,He was a Post-Doctoral Research Fellow with the Division of Biology, Caltech, and with the Institute of Neuroinformatics, University of Zürich and ETH Zürich. He is currently a Dual Professor with the Faculty of Science, University of Zürich, and with the Department of Information Technology and Electrical Engineering, ETH Zürich, Switzerland. He is also the Director of the Institute of Neuroinformatics (INI), University of Zürich and ETH Zürich. His research interests include the study of real and electronic neural processing systems, with a particular focus on spike-based learning and spike-based recurrent neural network dynamics. His research and development activities focus on the full custom hardware implementation of real-time sensory-motor systems using analog/digital neuromorphic circuits and emerging memory technologies. He received the ERC Starting Grant on “Neuromorphic Processors” in 2011, and the ERC Consolidator Grant on neuromorphic cognitive agents in 2016. He is a member of several technical committees of the IEEE Circuits and Systems Society and a Fellow of the European Research Council.

Speech Title: Brain-inspired Routing in Mixed-signal Neuromorphic Processors

For many edge-computing tasks that require real-time processing of sensory data and closed-loop interactions with the environment, conventional ANN accelerators cannot match the performance and efficiency of animal brains. One of the reasons for this gap is that neural computation in biological systems is organized in a way that is very different from the way it is implemented in today's deep network accelerators. In addition to being naturally event driven and asynchronous, neural computation in biological systems is tightly linked to the physics of their computing elements and to their temporal dynamics. Mixed-signal brain-inspired hardware architectures that emulate the biophysics of real neurons and synapses represent a promising technology for implementing alternative computing paradigms that bridge this gap. In this talk I will present hybrid analog/digital electronic circuits that directly emulate the biophysics of neural systems and present brain-inspired routing schemes multi-core architectures that support small-world network connectivity and minimize memory requirements.